Eric Smith eric at
Wed Jun 13 00:34:30 PDT 2007

Juergen wrote:
> I think the most important detail to conceive is the
> separation into rising and falling clock phases, i.e. the early and late
> stages of a cycle.

That's basically the right idea, but I'd like to elaborate a bit
on the details to avoid leading anyone astray.  In general all the
CPU registers are clocked on the same edge, which I'll call the active
edge.  Nothing in the core CPU is triggered by the inactive edge.

The Alto CPU circuitry can be divided into two types:

1)  Non-clocked (combinatorial) circuits, which perform some function
    continuously throughout a cycle.  Examples:  bus source selection,
    ALU function, shifter function.  The function can be considered to
    occur between two active edges of the clock, for the entire duration
    of that clock cycle.

2)  Edge-triggered circuits, which load data on an active edge.  These
    can load data either from another edge-triggered circuit, or from
    a combinatorial circuit.  Example:  the T register.  Aside from
    a small amount of setup and hold time, these registers can only
    be affected by the data that is present at their inputs at the
    clock edge.

In Altogether, I called these two types of functions "early" and
"late".  In hindsight it would have better for me to call them something
more accurately descriptive.  Perhaps static and edge functions, though
static might be confused by some readers with the unrelated C concept of
static functions.

      ______________                ______________                _____
_____/              \______________/              \______________/

     ^  <--------cycle 0 --------> ^  <----------cycle 1 ------> ^
     |                             |                             |
   edge 0                        edge 1                        edge 2

At edge 0, microinstruction 0 is loaded into the microinstruction
register.  The "early" functions of microinstruction 0, such as bus
source, ALU function, and shifter function selection happen continuously
throughout cycle 0, basically as fast as prop delays allow.

At edge 1, the "late" functions of microinstruction 0 happen (triggered
by the edge).  These include things like loading the T register.
Simultaneously, microinstruction 1 is loaded into the microinstruction
register, and the "early" functions of microinstruction 1 begin.


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